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description thegm72v28441at/alt is a synchronous dynamic random access memory comprised of 134,217,728 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided clock. the gm72v28441at/alt provides four banks of 8,388,608 word by 4 bit to realize high bandwidth with the clock frequency up to 125 mhz . features * pc100/pc66 compatible -8(125mhz) -7k(pc100,2-2-2),/-7j(pc100,3-2-2) -10k(pc66) * 3.3v single power supply * lvttl interface * max clock frequency 100/125 mhz * 4,096 refresh cycle per 64 ms two kind of refresh operation auto refresh/ self refresh * programmable burst access capability ; - sequence:sequential / interleave - length :1/2/4/8/fp * programmable cas latency : 2/3 * 4 banks can operate independently or simultaneously * burst read/burst write or burst read/single write operation capability * input and output masking by dqm input * one clock of back to back read or write command interval * synchronous power down and clock suspend capability with one clock latency for both entry and exit * jedec standard 54pin 400mil tsop ii package pin configuration pin name clk cke cs ras cas we a0~a9,a11 a10 / ap ba0/a13~ ba1/a12 dq0~dq3 dqm vccq vssq vcc vss nc clock clock enable chip select row address strobe column address strobe write enable address input address input or auto precharge bank select data input / data output data input / output mask v cc for dq v ss for dq power for internal circuit ground for internal circuit no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 jedec standard 400 mil 54 pin tsop ii (top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vcc nc vccq nc dq0 vssq nc nc vccq nc dq1 vssq nc vcc nc / we / cas / ras / cs ba0/a13 ba1/a12 a10,ap a0 a1 a2 a3 vcc vss nc vssq nc dq3 vccq nc nc vssq nc dq2 vccq nc vss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss gm72v28441at/alt 4 banks x 8m x 4bit synchronous dram this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.0/dec.99
gm72v28441at/alt rev. 1.0/dec.99 2 block diagram a0 to a13 a0 to a9,a11 a0 to a13 column address counter column address buffer row address counter refresh counter input buffer output buffer dq0 to dq3 control logic & timing generator clk cke dqm ras cas row decoder memory array bank 0 4096 row x 2048 column x 4bit column decoder sense amplifier & i/o bus row decoder memory array bank 1 4096 row x 2048 column x 4 bit column decoder sense amplifier & i/o bus row decoder memory array bank 2 4096 row x 2048 column x 4 bit column decoder sense amplifier & i/o bus row decoder memory array bank 3 4096 row x 2048 column x 4 bit column decoder sense amplifier & i/o bus cs we
gm72v28441at/alt rev. 1.0/dec.99 3 pin description pin name description clk (input pin) clk is the master clock input to this pin. the other input signals are referred at clk rising edge. cke (input pin) this pin determines whether or not the next clk is valid. if cke is high, the next clk rising edge is valid. if cke is low, the next clk rising edge is invalid. this pin is used for power-down and clock suspend modes. cs (input pin) when cs is low, the command input cycle becomes valid. when cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. although these pin names are the same as those of conventional drams , they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. ras, cas, and we (input pins) a0 ~ a11 (input pins) row address (ax0 to ax11) is determined by a0 to a11 level at the bank active command cycle clk rising edge. column address( ay0 to ay9,a11; gm72v28441at/alt,) is determined by a0 to a9,a11 level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged . but when a10 = low at the precharge command cycle, only the bank that is selected by a12/a13 (bs) is precharged . a12/a13 (input pin) a12/a13 are bank select signal (bs). the memory array of the the gm72v28441at/alt i s divided into bank 0, bank 1, bank2 and bank 3. . gm72v28441at/alt contain 4096-row x 2048-column x 4-bits. if a12 is low and if a13 is low, bank 0 is selected. if a12 is high and a13 is low, bank 1 is selected. if a12 is low and a13 is high, bank 2 is selected. if a12 is high and a13 is high, bank 3 is selected. dqm, dqmu/dqml (input pins) dqm, dqmu/dqml controls input/output buffers. - read operation: if dqm, dqmu/dqml is high, the output buffer becomes high-z. if the dqm, dqmu/dqml is low, the output buffer becomes low-z. - write operation: if dqm, dqmu/dqml is high, the previous data is held (the new data is not written). if dqm, dqmu/dqml is low, the data is written.
gm72v28441at/alt rev. 1.0/dec.99 4 command operation command truth table * notes : h: v ih , l: v il , x: v ih or v il , v: valid address input the synchronous dram recognizes the following commands specified by the cs, ras, cas, we and address pins. function ignore command symbol cke no operation burst stop in full page column address and read command read with auto- precharge write with auto- precharge row address strobe and bank active precharge all banks column address and write command cs ras cas we a12~ a13 a10 a0~ a11 desl nop bst read read a writ writ a actv pall h h h h h h h h h h x x x x x x x x x v h l l l l l l l l l x h h h h h h l l l x h h l l l l h h l x h l h h l l h l h x x x v v v v v x x x x x l h l h v h x x x x v v v v v x x n-1 n h x l l l l v v v mode register set mrs refresh ref/self precharge select bank pre h x l l h l v l x v ss and v ssq (power supply pins) ground is connected. (v ss is for the internal circuit and v ssq is for the output buffer.) nc no connection pins. description pin name v cc and v ccq (power supply pins) 3.3 v is applied. (v cc is for the internal circuit and v ccq is for the output buffer.) dq0 ~ dq3 (i/o pins) data is input and output from these pins. these pins are the same as those of a conventional dram. pin description(continued)
gm72v28441at/alt rev. 1.0/dec.99 5 burst stop in full page [bst] : this command stops a full-page burst operation ( burst length= full-page(2048 ; gm72v28441at/alt )), and is illegal otherwise. full page burst continues until this command is input. when data input/output is completed for full-page of data, it automatically returns to the start address, and input/output is performed repeatedly. column address strobe and read command [read]: this command starts a read operation. in addition, the start address of burst read is determined by the column address ( ay0 to ay9,ay11; gm72v28441at/alt ) and the bank select address (a12/a13). after the read operation, the output buffer becomes high-z. read with auto- precharge [read a]: this command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. when the burst length is full-page, this command is illegal. column address strobe and write command [writ]: this command starts a write operation. when the burst write mode is selected, the column address ( ay0 to ay9,ay11; gm72v28441at/alt ) and the bank select address (a12/a13) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address ( ay0 to ay9,ay11; gm72v28441at/alt ) and the bank select address (a12/a13). write with auto- precharge [writ a]: this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. when the burst length is full-page, this command is illegal. row address strobe and bank activate [actv]: this command activates the bank that is selected by a12/a13(bs) and determines the row address (ax0 to ax11). if a12 is low and if a13 is low, bank 0 is activated. if a12 is high and a13 is low, bank 1 is activated. if a12 is low and a13 is high, bank 2 is activated. if a12 is high and a13 is high, bank 3 is activated. precharge selected bank [pre]: this command starts precharge operation for the bank selected by a12/a13. if a12 is low and if a13 is low, bank 0 is selected. if a12 is high and a13 is low, bank 1 is selected. if a12 is low and a13 is high, bank 2 is selected. if a12 is high and a13 is high, bank 3 is selected. precharge all banks [pall]: this command starts a precharge operation for all banks. refresh [ref/self]: this command starts the refresh operation. there are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. for details, refer to the cke truth table section. mode register set [mrs]: synchronous dram has a mode register that defines how it operates. the mode register is specified by the address pins (a0 to a11) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. ignore command [desl]: when this command is set (cs is high), the synchronous dram ignores command input at the clock. however, the internal status is held. no operation [nop]: this command is not an execution command. however, the internal operations continue.
gm72v28441at/alt rev. 1.0/dec.99 6 dqm truth table function write enable/output enable write inhibit/output disable symbol enb mask n-1 cke dqm n h h x x l h the gm72v28441at/alt can mask input/output data by means of dqm. during reading, the output buffer is set to low-z by setting dqm to low, enabling data output. on the other hand, when dqm is set to high, the output buffer becomes high-z, disabling data output. during writing, data is written by setting dqm to low. when dqm is set to high, the previous data is held (the new data is not written). desired data can be masked during burst read or burst write by setting dqm. for details, refer to the dqm control section of the gm72v28441at/alt operating instructions. * notes : h: v ih , l: v il , x: v ih or v il . write : l did is needed. read : l dod is needed.
gm72v28441at/alt rev. 1.0/dec.99 7 write suspend and writ a suspend: in this mode, external signals are not accepted. however, the internal state is held. clock suspend: during clock suspend mode, keep the cke to low. clock suspend mode exit : the synchronous dram exits from clock suspend mode by setting cke to high during the clock suspend state. idle: in this state, all banks are not selected, and completed precharge operation. clock suspend mode entry: the synchronous dram enters clock suspend mode from active mode by setting cke to low. the clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend: this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read a suspend: the data being output is held (and continues to be output). * notes : h: v ih , l: v il , x: v ih or v il . power down idle power down entry self refresh exit power down exit h l l l h h l l h h h x self refresh ( selfx) h l h x x x x h h h x h h h x l l h h x x x x l h x x x x h current state active cke any clock suspend idle idle clock suspend mode entry clock suspend clock suspend mode exit auto-refresh command self-refresh entry h l l h h l l h h l h x x l l x x x l l x x x l l x x x h h x x x x x function ( ref) ( self) n -1 n cs ras cas we address cke truth table
gm72v28441at/alt rev. 1.0/dec.99 8 self-refresh exit[selfx]: when this command is executed during self-refresh mode, the synchronous dram can exit from self-refresh mode. after exiting from self-refresh mode, the synchronous dram enters the idle state. power down mode entry: when this command is executed during the idle state, the synchronous dram enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. power down exit: when this command is executed at the power down mode, the synchronous dram can exit from power down mode. after exiting from power down mode, the synchronous dram enters the idle state. auto-refresh command[ref]: when this command is input from the idle state, the synchronous dram starts auto-refresh operation. (the auto-refresh is the same as the cbr refresh of conventional drams .) during the auto-refresh operation, refresh address and bank select address are generated inside the synchronous dram. for every auto-refresh cycle, the internal address counter is updated. accordingly, 4,096 times are required to refresh the entire memory. before executing the auto- refresh command, all the banks must be in the idle state. in addition, since the precharge for all banks is automatically performed after auto- refresh, no precharge command is required after auto-refresh. self-refresh entry[self]: when this command is input during the idle state, the synchronous dram starts self-refresh operation. after the execution of this command, self-refresh continues while cke is low. since self-refresh is performed internally and automatically, external refresh operations are unnecessary. function truth table the following table shows the operations that are performed when each command is issued in each mode of the synchronous dram. current state precharge cs ras cas we address h x x x x l h h h x l h h l x l h l h ba, ca, a10 l h l l ba, ca, a10 l l h h ba, ra l l h l ba, a10 command operation desl nop bst read/read a writ/writ a actv pre, pall enter idle after t rp enter idle after t rp nop illegal illegal illegal nop
gm72v28441at/alt rev. 1.0/dec.99 9 function truth table (continued) current state precharge cs ras cas we address h x x x x l h h h x l h h l x l h l h ba, ca, a10 l h l l ba, ca, a10 l l h h ba, ra l l h l ba, a10 l l l h x l l l l mode command operation desl nop bst read/read a writ/writ a actv pre, pall ref, self mrs nop nop nop illegal illegal bank and row active nop refresh mode register set l l l h x l l l l mode ref, self mrs illegal illegal idle row active h x x x x l h h h x l h h l x l h l h ba, ca, a10 l l h h ba, ra l l h l ba, a10 l l l h x desl nop bst read/read a actv pre, pall ref, self nop nop nop begin read precharge illegal l l l l mode mrs illegal l h l l ba, ca, a10 writ/writ a begin write other bank active illegal on same bank *3
gm72v28441at/alt rev. 1.0/dec.99 10 function truth table (continued) current state read cs ras cas we address l h h h x l h h l x l h l h ba, ca, a10 l h l l ba, ca, a10 l l h h ba, ra l l h l ba, a10 l l l h x l l l l mode command operation nop bst read/read a writ/writ a actv pre, pall ref, self mrs continue burst to end burst stop to full page term burst read/start write term burst read and precharge illegal illegal h x x x x desl continue burst to end read with auto- precharge h x x x x l h h h x l h h l x l h l l ba, ca, a10 l l h h ba, ra l l h l ba, a10 desl nop bst writ/writ a actv pre, pall continue burst to end and precharge continue burst to end and precharge illegal illegal l l l h x ref, self illegal l h l h ba, ca, a10 read/read a illegal illegal other bank active illegal on same bank *3 continue burst read to cas latency and new read l l l l mode mrs illegal other bank active illegal on same bank *3
gm72v28441at/alt rev. 1.0/dec.99 11 function truth table (continued) current state write cs ras cas we address l h h h x l h h l x l h l h ba, ca, a10 l h l l ba, ca, a10 l l h h ba, ra l l h l ba, a10 l l l h x l l l l mode command operation nop bst read/read a writ/writ a actv pre, pall ref, self mrs continue burst to end burst stop on full page term burst and new write illegal illegal h x x x x desl continue burst to end write with auto- precharge h x x x x l h h h x l h h l x l h l l ba, ca, a10 l l h h ba, ra l l h l ba, a10 desl nop bst writ/writ a actv pre, pall continue burst to end and precharge continue burst to end and precharge illegal illegal l l l h x ref, self illegal l h l h ba, ca, a10 read/read a illegal illegal other bank active illegal on same bank *3 term burst and new read l l l l mode mrs illegal term burst write and precharge *2 other bank active illegal on same bank *3
gm72v28441at/alt rev. 1.0/dec.99 12 from [precharge] to [desl], [nop] or [bst]: when these commands are executed, the synchronous dram enters the idle state after t rp has elapsed from the completion of precharge from [idle] to [desl], [nop], [bst], [pre] or [pall]: these commands result in no operation. to [actv]: the bank specified by the address pins and the row address is activated. to [ref], [self]: the synchronous dram enters refresh mode (auto-refresh or self-refresh). to [mrs]: the synchronous dram enters the mode register set cycle. from [row active] to [desl], [nop] or [bst]: these commands result in no operation. to [read], [read a]: a read operation starts. (however, an interval of t rcd is required.) to [writ], [writ a]: a write operation starts. (however, an interval of t rcd is required.) to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands set the synchronous dram to precharge mode. (however, an interval of t ras is required.) function truth table (continued) current state refresh (auto-refresh) cs ras cas we address l h h h x l h h l x l h l h ba, ca, a10 l h l l ba, ca, a10 l l h h ba, ra l l h l ba, a10 l l l h x l l l l mode command operation nop bst read/read a writ/writ a actv pre, pall ref, self mrs enter idle after t rc enter idle after t rc illegal illegal illegal h x x x x desl enter idle after t rc illegal illegal illegal * notes : 1. h: v ih , l: v il , x: v ih or v il . the other combinations are inhibit. 2. an interval of t rwl is required between the final valid data input and the precharge command. 3. if t rrd is not satisfied, this operation is illegal. 4. ba:bank address, ra:row address, ca:column address
gm72v28441at/alt rev. 1.0/dec.99 13 from [write with auto-precharge] to [desl], [nop]: these commands continue write operations until the burst operation is completed, and the synchronous dram then enters precharge mode. to [actv]: this command makes the other bank active. (however, an interval of t rc is required.) attempting to make the currently active bank active results in an illegal command. to [desl], [nop], [bst]: after an auto- refresh cycle (after t rc ), the synchronous dram automatically enters the idle state. from [refresh] from [write] to [desl], [nop]: these commands continue write operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: these commands stop a burst and start a read cycle. to [writ], [writ a]: these commands stop a burst and start the next write cycle. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop burst write and the synchronous dram then enters precharge mode. from [read] from [read with auto-precharge] to [desl], [nop]: these commands continue read operations until the burst operation is completed, and the synchronous dram then enters precharge mode. to [actv]: this command makes other banks bank-active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [desl], [nop]: these commands continue read operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: data output by the previous read command continues to be output. after cas latency, the data output resulting from the next command will start. to [writ], [writ a ] : these commands stop a burst read, and start a write cycle. to [actv]: this command makes other banks bank-active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop a burst read, and the synchronous dram enters precharge mode.
gm72v28441at/alt rev. 1.0/dec.99 14 absolute maximum ratings notes : 1. respect to v ss symbol value unit note parameter v t -0.5 to vcc +0.5 (<= 4.6 (max)) v 1 voltage on any pin relative to v ss v cc -0.5 to +4.6 v 1 supply voltage relative to v ss i out 50 ma short circuit output current p t 1.0 w power dissipation topr 0 to +70 c operating temperature tstg -55 to +125 c storage temperature notes : 1. all voltage referred to v ss . 2. v ih (max) = 5.6v for pulse width <= 3ns 3. v il (min) = -2.0v for pulse width <= 3ns recommended dc operating conditions ( ta = 0 to + 70c) symbol min unit note v cc , v ccq v 1 v ss , v ssq v input high voltage v ih v 1, 2 input low voltage v il v 1,3 supply voltage parameter max 3.0 3.6 0 0 2.0 vcc + 0.3 -0.3 0.8
gm72v28441at/alt rev. 1.0/dec.99 15 dc characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/-0.3 v, v ss , v ssq = 0 v) parameter symbol unit test conditions notes operating current standby current in power down i cc2p self refresh current i cc6 ma v ih >=v cc - 0.2 v il <=0.2v 7 burst length= 1 t rc = min 1, 2, 3 cke = v il , t ck = 12 ns 5 i cc1 ma ma standby current in power down (input signal stable) i cc2ps cke=v il , t ck = infinity 6 ma standby current in non power down (cas latency=2) i cc2n cke,cs = v ih , t ck = 12ns 4 ma standby current in non power down (input signal stable) i cc2ns cke,cs = v ih , t ck = infinity 4 ma active standby current in power down i cc3p cke = v il , t ck = 12 ns , dq = high-z ma active standby current in power down (input signal stable) i cc3ps cke = v il , t ck = infinity 2,6 ma active standby current in non power down i cc3n cke,cs = v ih , t ck = 12 ns , dq = high-z 1,2,4 ma active standby current in non power down (input signal stable) i cc3ns cke,cs = v ih , t ck = infinity 2,9 ma burst operating current i cc4 t ck = min bl = 4 1,2,3 ma ( cl= 2 ) i cc4 ma ( cl= 3 ) refresh current t rc = min 3 i cc5 ma 7,8 6,8 1,2,5 - 8 max - 10 k max 2 2 110 1010 2 2 1 1 15 15 15 15 5 5 30 30 30 30 120 90 130 120 230 190 0.8 0.8 0.4 0.4 5 5 2 2 - 7 k max - 7 j 110 1 15 15 5 30 30 90 120 220 0.8 0.4 5 2 2 max 110 1 15 15 5 30 30 120 120 220 0.8 0.4 5
gm72v28441at/alt rev. 1.0/dec.99 16 notes : 1. i cc depends on output load condition when the device is selected. i cc ( max) is specified at the output open condition. 2. one bank operation. 3. addresses are changed once per one cycle. 4. addresses are changed once per two cycles. 5. after power down mode, clk operating current. 6. after power down mode, no clk operating current. 7. after self refresh mode set, self refresh current. 8. l-version. 9. input signals are v ih or v il fixed. capacitance ( ta = 25c, v cc , v ccq = 3.3 v +/- 0.3 v) notes : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. dqm, dqmu/dqml = v ih to disable dout . 3. this parameter is sampled and not 100% tested. 4. measured with 1.4 v bias and 200mv swing at the pin under measurement. input leakage current i li ua 0<= vin<=v cc output leakage current i lo ua 0<= vout <=v cc dq = disable output high voltage v oh v i oh = -2 ma output low voltage v ol v i ol =2 ma -1 1 -1.5 1.5 - 0.4 parameter symbol unit test conditions notes min max - 8, - 7 k, -7j, -10k 2.4 - parameter input capacitance (clk) input capacitance (signals) output capacitance (dq) symbol c i1 c i2 c o min. 2.5 2.5 4.0 max. 4 5 6.5 unit pf pf pf notes 1, 3, 4 1, 3, 4 1, 2, 3, 4
gm72v28441at/alt rev. 1.0/dec.99 17 ac characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) symbol unit notes t ck t ck parameter system clock cycle time ( cl=2) ( cl=3) ns 1 t ckh ns 1 clk high pulse width t ckl ns 1 clk low pulse width t ac t ac access time from clk ( cl=2) ( cl=3) ns 1, 2 t oh ns 1, 2 data-out hold time t lz ns 1, 2, 3 clk to data-out low impedance t hz clk to data-out high impedance ( cl = 2,3 ) ns 1, 4 t ds ns 1 data-in setup time t dh ns 1 data-in hold time t as ns 1 address setup time t ah ns 1 address hold time t ces ns 1, 5 cke setup time t cesp ns 1 cke setup time for power down exit t ceh ns 1 cke hold time t cs ns 1 command (cs, ras, cas, we, dqm) setup time t rc ns 1 ref/active to ref/active command period t ch ns 1 command (cs, ras, cas, we, dqm) hold time t ras ns 1 active to precharge command period t rcd ns 1 active command to column command (same bank) t rp ns 1 precharge to active command period - 8 min max 8 - 12 - - 10 k min max 10 - 15 - 3 - 3 - 3 - 3 - - 6 - 6 - 8 - 9 3 - 3 - 2 - 2 - - 6 - 7 2 - 2 - 1 - 1 - 2 - 2 - 1 - 1 - 2 - 2 - 2 - 2 - 1 - 1 - 2 - 2 - 72 - 90 - 1 - 1 - 48 120000 60 120000 20 - 30 - 20 - 30 - - 7 k min max 10 - 10 - 3 - 3 - - 6 - 6 3 - 2 - - 6 2 - 1 - 2 - 1 - 2 - 2 - 1 - 2 - 70 - 1 - 50 120000 20 - 20 - - 7 j min max 10 - 15 - 3 - 3 - - 6 - 8 3 - 2 - - 6 2 - 1 - 2 - 1 - 2 - 2 - 1 - 2 - 70 - 1 - 50 120000 20 - 20 -
gm72v28441at/alt rev. 1.0/dec.99 18 ac characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) (continued) test condition input and output-timing reference levels: 1.4v input waveform and output load: see following figures 20% t t t t 0.4 v 2.4 v i/o 80% open input c l notes : 1. ac measurement assumes t t = 1ns. reference level for timing of input signals is 1.40v. if t t is longer than 1ns,transition time compensation should be considered. 2. access time is measured at 1.40v. load condition is c l = 50pf without termination. 3. t lz (min)defines the time at which the outputs achieves the low impedance state. 4. t hz (max)defines the time at which the outputs achieves the high impedance state. 5. t ces define cke setup time to cke rising edge except power down exit command. symbol notes parameter 1 t rrd 1 active (a) to active (b) command period t ref refresh period t rwl write recovery or data-in to precharge lead time unit ns ns ms - 7 k min max 10 - 20 - - 64 - 7 j min max 10 - 20 - - 64 - 10 k min max 15 - 20 - - 64 - 8 min max 8 - 16 - - 64
gm72v28441at/alt rev. 1.0/dec.99 19 relationship between frequency and minimum latency notes l rcd 1 active command to column command (same bank) l rc = [ l ras + l rp ], 1 active command to active command (same bank) l ras active command to precharge command (same bank) l rp 1 precharge command to active command (same bank) l rwl 1 write recovery or last data-in to precharge command (same bank) l rrd 1 active command to active command (different bank) l srex self refresh exit time l apw = [ l rwl + l rp ], 1 last data in to active command (auto precharge , same bank) l sec = [ l rc ] self refresh exit to command input l hzp precharge command to high impedance l hzp ( cl=2) ( cl=3) l apr last data out to active command (auto precharge ) (same bank) l ep last data out to precharge (early precharge ) l ep ( cl=2) ( cl=3) l ccd column command to column command l wcd write command to data in latency l did dqm to data in l dod dqm to data out l pec power down exit to command input l cle cke to clk disable l rsa register set to active command l cdd parameter t ck ( ns ) frequency(mhz) 1 cs to command disable symbol -7 j 100 2 7 5 10 2 1 2 1 3 7 - 3 1 - - 2 1 0 0 2 1 1 1 0 -8 125 3 9 6 8 3 1 2 1 4 9 - 3 1 - -2 1 0 0 2 1 1 1 0 83 2 6 4 12 2 1 2 2 3 6 2 3 1 -1 -2 1 0 0 2 1 1 1 0 66 2 6 4 15 2 1 2 2 3 6 2 3 1 -1 - 2 1 0 0 2 1 1 1 0 100 2 7 5 10 2 1 2 1 3 7 2 3 1 - 1 - 2 1 0 0 2 1 1 1 0 -7 k 100 2 7 5 10 2 1 2 1 3 7 2 3 1 - 1 - 2 1 0 0 2 1 1 1 0 -10 k 100 3 9 6 10 3 1 2 2 5 9 - 3 1 - - 2 1 0 0 2 1 1 1 0 66 2 6 4 15 2 1 2 2 3 6 2 3 1 -1 - 2 1 0 0 2 1 1 1 0
gm72v28441at/alt rev. 1.0/dec.99 20 relationship between frequency and minimum latency notes : 1. l rcd to l rrd are recommended value. symbol notes l bsr burst stop to output valid data hold l bsr ( cl=2) ( cl=3) l bsh burst stop to output high impedance l bsh ( cl=2) ( cl=3) l bsw burst stop to write data ignore parameter t ck ( ns ) frequency(mhz) - 7 k - 7 j - 8 125 8 - 2 - 3 0 83 12 1 2 2 3 0 100 10 - 2 - 3 0 66 15 1 2 2 3 0 100 10 1 2 2 3 0 100 10 1 2 2 3 0 - 10 k 100 10 - 2 - 3 0 66 15 1 2 2 3 0
gm72v28441at/alt rev. 1.0/dec.99 21 package dimensions gm72v28441at/alt series (ttp-54d) unit: (mm) 0.145 + 0.05 0.125 + 0.04 0.91 max 0.30 22.72 max 22.22 54 28 1 27 10.16 0.80 0.13 m +0.10 - 0.05 0.28 + 0.05 1.20 max 0.10 dimension including the plating thickness base material dimension 0.68 0.50 + 0.10 0.80 preliminary hitachi code eiaj code jedec code weight(reference value) ttp-54d - - 0.53 g 11.76 + 0.20 0.13 + 0.05 0 ~ 5 ?

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